#ifndef DP83848J_REGS_H_
#define DP83848J_REGS_H_



#define DP83848_ID_VENDOR           0x080017
#define DP83848J_ID_MODEL           0x0009
#define DP83848C_ID_MODEL           0x000A


/* В данном файле определены Device Specific регистры для
 * PHY DP83848J и часть их бит */
#define DP83848_REGADDR_PHYSTS      0x10 /* PHY Status Register */
#define DP83848_REGADDR_MICR        0x11 /* C: MII Interrupt Control Register */
#define DP83848_REGADDR_MISR        0x12 /* C: MII Interrupt Status Register */
#define DP83848_REGADDR_FCSCR       0x14 /* False Carrier Sense Counter Register */
#define DP83848_REGADDR_RECR        0x15 /* Receive Error Counter Register */
#define DP83848_REGADDR_PCSR        0x16 /* PCS Sub-Layer Configuration and Status Register */
#define DP83848_REGADDR_RBR         0x17 /* RMII and Bypass Register */
#define DP83848_REGADDR_LEDCR       0x18 /* LED Direct Control Register */
#define DP83848_REGADDR_PHYCR       0x19 /* Phy Control Register */
#define DP83848_REG_10BTSCR         0x1A /* 10Base-T Status/Control Register */
#define DP83848_REG_CDCTRL1         0x1B /* CD Test Control Register and BIST Extensions Register */
#define DP83848_REG_EDCR            0x1D /* Energy Detect Control Register */


/****** PHY Status Register (PHYSTS) ******************************************/
#define DP83848_REGFLD_PHYSTS_MDIX_MODE             (0x0001UL << 14) /* (RO) MDI-X mode as reported by the Auto-Negotiation logic (1 - MDI pairs swapped)*/
#define DP83848_REGFLD_PHYSTS_RECV_ERR              (0x0001UL << 13) /* (RC/LH) Receive Error Latch */
#define DP83848_REGFLD_PHYSTS_POLARITY              (0x0001UL << 12) /* (RO) Polarity Status (= bit 4 of 10BTSCR) (1 - Inverted polarity detected). Clear on read 10BTSCR  */
#define DP83848_REGFLD_PHYSTS_FALSE_CARRIER_SENSE   (0x0001UL << 11) /* (RC/LH) False Carrier Sense Latch  */
#define DP83848_REGFLD_PHYSTS_SIGNAL_DETECT         (0x0001UL << 10) /* (RO/LL) 100Base-TX unconditional Signal Detect from PMD */
#define DP83848_REGFLD_PHYSTS_DESCRAMPLER_LOCK      (0x0001UL <<  9) /* (RO/LL) 100Base-TX Descrambler Lock from PMD */
#define DP83848_REGFLD_PHYSTS_PAGE_RECVD            (0x0001UL <<  8) /* (RO) Link Code Word Page Received */
#define DP83848_REGFLD_PHYSTS_REMOTE_FAULT          (0x0001UL <<  6) /* (RO) Remote Fault condition detected (cleared or BMSR read or reset) */
#define DP83848_REGFLD_PHYSTS_JABBER_DETECT         (0x0001UL <<  5) /* (RO) Jabber condition detected. */
#define DP83848_REGFLD_PHYSTS_AUTONEG_CPL           (0x0001UL <<  4) /* (RO)  Auto-Negotiation complete */
#define DP83848_REGFLD_PHYSTS_LOOPBACK_STATUS       (0x0001UL <<  3) /* (RO)  Loopback Status (1 - enabled) */
#define DP83848_REGFLD_PHYSTS_DUPLEX_STATUS         (0x0001UL <<  2) /* (RO)  Duplex Status (1 - full, 0 - half) */
#define DP83848_REGFLD_PHYSTS_SPEED_STATUS          (0x0001UL <<  1) /* (RO)  Speed10 Status (1 - 10 Mbit/s, 0 - 100 Mbit/s) */
#define DP83848_REGFLD_PHYSTS_LINK_STATUS           (0x0001UL <<  0) /* (RO)  Link Status (1 - established) */
#define DP83848_REGMSK_PHYSTS_RESERVED              (0x8080)


/****** MII Interrupt Control Register (MICR) (DP83848C only) *****************/
#define DP83848_REGFLD_MICR_TINT                    (0x0001UL <<  2) /* (RW) Test Interrupt: Force PHY to generate an interrupt */
#define DP83848_REGFLD_MICR_INTEN                   (0x0001UL <<  1) /* (RW) Enable event based interrupts */
#define DP83848_REGFLD_MICR_INT_OE                  (0x0001UL <<  0) /* (RW) Enable interrupt events to signal through the PWRDOWN_INT pin  */
#define DP83848_REGMSK_MICR_RESERVED                (0xFFF8UL)


/****** MII Interrupt Status and Misc. Control Register (MISR) (DP83848C only) */
#define DP83848_REGFLD_MISR_ED_INT                  (0x0001UL << 14) /* (RC) Energy Detect interrupt */
#define DP83848_REGFLD_MISR_LINK_INT                (0x0001UL << 13) /* (RC) Change of Link Status interrupt */
#define DP83848_REGFLD_MISR_SPD_INT                 (0x0001UL << 12) /* (RC) Change of speed status interrupt */
#define DP83848_REGFLD_MISR_DUP_INT                 (0x0001UL << 11) /* (RC) Change of duplex status interrupt */
#define DP83848_REGFLD_MISR_ANC_INT                 (0x0001UL << 10) /* (RC) Auto-Negotiation Complete interrupt */
#define DP83848_REGFLD_MISR_FHF_INT                 (0x0001UL <<  9) /* (RC) False Carrier Counter half-full interrupt */
#define DP83848_REGFLD_MISR_RHF_INT                 (0x0001UL <<  8) /* (RC) Receive Error Counter half-full interrupt */
#define DP83848_REGFLD_MISR_ED_INT_EN               (0x0001UL <<  6) /* (RW) Enable Interrupt on energy detect event */
#define DP83848_REGFLD_MISR_LINK_INT_EN             (0x0001UL <<  5) /* (RW) Enable Interrupt on change of link status. */
#define DP83848_REGFLD_MISR_SPD_INT_EN              (0x0001UL <<  4) /* (RW) Enable Interrupt on change of speed status */
#define DP83848_REGFLD_MISR_DUP_INT_EN              (0x0001UL <<  3) /* (RW) Enable Interrupt on change of duplex status */
#define DP83848_REGFLD_MISR_ANC_INT_EN              (0x0001UL <<  2) /* (RW) Enable Interrupt on Auto-negotiation complete event */
#define DP83848_REGFLD_MISR_FHF_INT_EN              (0x0001UL <<  1) /* (RW) Enable Interrupt on False Carrier Counter Register half-full event */
#define DP83848_REGFLD_MISR_RHF_INT_EN              (0x0001UL <<  0) /* (RW) Enable Interrupt on Receive Error Counter Register half-full event */
#define DP83848_REGMSK_MISR_RESERVED                (0x8080UL)


/****** False Carrier Sense Counter Register (FCSCR) **************************/
#define DP83848_REGFLD_FCSCR_FCSCNT                 (0x00FFUL <<  0) /* (RC) False Carrier Event Counter (increment on every false carrier event) */
#define DP83848_REGMSK_FCSCR_RESERVED               (0xFF00UL)


/****** Receiver Error Counter Register (RECR) *******************************/
#define DP83848_REGFLD_RECR_RXERCNT                 (0x00FFUL <<  0) /* (RC) Symbol Error During Carrier counter */
#define DP83848_REGMSK_RECR_RESERVED                (0xFF00UL)


/****** 100 Mb/s PCS Configuration and Status Register (PCSR) *****************/
#define DP83848_REGFLD_PCSR_FREE_CLK                (0x0001UL << 11) /* (RW) C: Receive Clock, J: must be 0 */
#define DP83848_REGFLD_PCSR_TQ_EN                   (0x0001UL << 10) /* (RW) 100Mbs True Quiet Mode Enable */
#define DP83848_REGFLD_PCSR_SD_FORCE_PMA            (0x0001UL <<  9) /* (RW) Signal Detect Force PMA */
#define DP83848_REGFLD_PCSR_SD_OPTION               (0x0001UL <<  8) /* (RW) Signal Detect Option (1 - Enhanced, 0 - Reduced) */
#define DP83848_REGFLD_PCSR_DESC_TIME               (0x0001UL <<  7) /* (RW) Descrambler Timeout (1 - 2ms, 0 - 722us) */
#define DP83848_REGFLD_PCSR_FORCE_100_OK            (0x0001UL <<  5) /* (RW) Forces 100Mb/s Good Link */
#define DP83848_REGFLD_PCSR_NRZI_BYPASS             (0x0001UL <<  2) /* (RW) NRZI Bypass Enable */
#define DP83848_REGMSK_PCSR_RESERVED                (0xF05BUL)


/****** RMII and Bypass Register (RBR) ****************************************/
#define DP83848_REGFLD_RBR_RMII_MODE                (0x0001UL <<  5) /* (RW, strap) RMII mode (0 - MII, 1 - RMII) */
#define DP83848_REGFLD_RBR_RMII_REV1_0              (0x0001UL <<  4) /* (RW) RMII version 1.0 (0 - version 1.2) */
#define DP83848_REGFLD_RBR_RX_OVF_STS               (0x0001UL <<  3) /* (RO) RX FIFO Over Flow Status */
#define DP83848_REGFLD_RBR_RX_UNF_STS               (0x0001UL <<  2) /* (RO) RX FIFO Under Flow Status */
#define DP83848_REGFLD_RBR_ELAST_BUF                (0x0003UL <<  0) /* (RW) Receive Elasticity Buffer (for frequency variation tolerance between the 50-MHz RMII clock and the recovered data) */
#define DP83848_REGMSK_RBR_RESERVED                 (0xFFC0UL)

#define DP83848_REGFLDVAL_RBR_ELAST_BUF_14BIT       0 /* 14 bit tolerance (up to 16800 byte packets at ±50 ppm) */
#define DP83848_REGFLDVAL_RBR_ELAST_BUF_2BIT        1 /* 2 bit tolerance (up to 2400 byte packets at ±50 ppm) */
#define DP83848_REGFLDVAL_RBR_ELAST_BUF_6BIT        2 /* 6 bit tolerance (up to 7200 byte packets at ±50 ppm) */
#define DP83848_REGFLDVAL_RBR_ELAST_BUF_10BIT       3 /* 10 bit tolerance (up to 12000 byte packets at ±50 ppm) */


/****** LED Direct Control Register (LEDCR) ***********************************/
#define DP83848_REGFLD_LEDCR_DRV_SPDLED             (0x0001UL <<  5) /* (RW) Drive value of SPDLED bit onto LED_SPEED output */
#define DP83848_REGFLD_LEDCR_DRV_LNKLED             (0x0001UL <<  4) /* (RW) Drive value of LNKLED bit onto LED_LINK output */
#define DP83848_REGFLD_LEDCR_DRV_ACTLED             (0x0001UL <<  3) /* (RW) C: Drive value of ACTLED bit onto LED_ACT/LED_COL outpu */
#define DP83848_REGFLD_LEDCR_SPDLED                 (0x0001UL <<  2) /* (RW) Value to force on LED_SPEED output */
#define DP83848_REGFLD_LEDCR_LNKLED                 (0x0001UL <<  1) /* (RW) Value to force on LED_LINK output */
#define DP83848_REGFLD_LEDCR_ACTLED                 (0x0001UL <<  0) /* (RW) Value to force on LED_ACT/LED_COL output */
#define DP83848_REGMSK_LEDCR_RESERVED               (0xFFC0UL)


/****** PHY Control Register (PHYCR) ******************************************/
#define DP83848_REGFLD_PHYCR_MDIX_EN                (0x0001UL << 15) /* (RW, strap) Auto-MDIX Enable */
#define DP83848_REGFLD_PHYCR_FORCE_MDIX             (0x0001UL << 14) /* (RW) Force MDI pairs to cross */
#define DP83848_REGFLD_PHYCR_PAUSE_RX               (0x0001UL << 13) /* (RW) Pause Receive Negotiated */
#define DP83848_REGFLD_PHYCR_PAUSE_TX               (0x0001UL << 12) /* (RW) Pause Transmit Negotiated */
#define DP83848_REGFLD_PHYCR_BIST_FE                (0x0001UL << 11) /* (RWSC) BIST Force Error */
#define DP83848_REGFLD_PHYCR_PSR_15                 (0x0001UL << 10) /* (RWSC) BIST Sequence select (1 - PSR15, 0 - PSR9) */
#define DP83848_REGFLD_PHYCR_BIST_STATUS            (0x0001UL <<  9) /* (RO LL) BIST Test Status (1 - pass, 0 - fail) */
#define DP83848_REGFLD_PHYCR_BIST_START             (0x0001UL <<  8) /* (RW) BIST Start */
#define DP83848_REGFLD_PHYCR_BP_STRETCH             (0x0001UL <<  7) /* (RW) Bypass LED Stretching */
#define DP83848_REGFLD_PHYCR_LED_CNFG               (0x0003UL <<  5) /* (RW, strap) LED Configuration mode (j: mode0/1, c: mode0/1/3) */
#define DP83848_REGFLD_PHYCR_PHYADDR                (0x001FUL <<  0) /* (RW, strap) PHY address for port */


/****** 10BASE-T Status/Control Register (10BTSCR) ****************************/
#define DP83848_REGFLD_10BTSCR_10BT_SERIAL          (0x0001UL << 15) /* (RW) C: 10Base-T Serial Mode (SNI) */
#define DP83848_REGFLD_10BTSCR_SQUELCH              (0x0007UL <<  9) /* (RW) Squelch Configuration */
#define DP83848_REGFLD_10BTSCR_LOOPBACK_10_DIS      (0x0001UL <<  8) /* (RW) 10Base-T Loopback Disable */
#define DP83848_REGFLD_10BTSCR_LP_DIS               (0x0001UL <<  7) /* (RW) Normal Link Pulse Disable */
#define DP83848_REGFLD_10BTSCR_FORCE_LINK_10        (0x0001UL <<  6) /* (RW) Forced Good 10Mb Link. */
#define DP83848_REGFLD_10BTSCR_POLARITY             (0x0001UL <<  4) /* (RW) 10Mb Polarity Status */
#define DP83848_REGFLD_10BTSCR_HEARTBEAT_DIS        (0x0001UL <<  1) /* (RW) Heartbeat Disable (half-duplex 10Mb mode) */
#define DP83848_REGFLD_10BTSCR_JABBER_DIS           (0x0001UL <<  0) /* (RW) Jabber Disable (10BASE-T) */
#define DP83848_REGMSK_10BTSCR_RESERVED             (0x702CUL)


/****** CD Test and BIST Extensions Register (CDCTRL1) ************************/
#define DP83848_REGFLD_CDCTRL1_BIST_ERROR_COUNT     (0x00FFUL <<  8) /* (RW) Counts number of errored data nibbles during Packet BIST */
#define DP83848_REGFLD_CDCTRL1_BIST_COUNT_MODE      (0x0001UL <<  5) /* (RW) Packet BIST Continuous Mode */
#define DP83848_REGFLD_CDCTRL1_CDPATTEN_10          (0x0001UL <<  4) /* (RW) CD Pattern Enable for 10Mb */
#define DP83848_REGFLD_CDCTRL1_10MEG_PATT_GAP       (0x0001UL <<  2) /* (RW) Defines gap between data or NLP test sequences (1 - 15us, 0 - 10us) */
#define DP83848_REGFLD_CDCTRL1_CDPATTSEL            (0x0003UL <<  0) /* (RW) CD Pattern Select (0 - Data EOP0 seq, 1 - Data EOP1 seq, 2 - NLP, 3 - Manchester) */
#define DP83848_REGMSK_CDCTRL1_RESERVED             (0x00C8UL)


/****** Energy Detect Control (EDCR) ****************************/
#define DP83848_REGFLD_EDCR_ED_EN                   (0x0001UL << 15) /* (RW) Energy Detect Enable */
#define DP83848_REGFLD_EDCR_ED_AUTO_UP              (0x0001UL << 14) /* (RW) Energy Detect Automatic Power Up */
#define DP83848_REGFLD_EDCR_ED_AUTO_DOWN            (0x0001UL << 13) /* (RW) Energy Detect Automatic Power Down */
#define DP83848_REGFLD_EDCR_ED_MAN                  (0x0001UL << 12) /* (RW SC) Energy Detect Manual Power Up/Down */
#define DP83848_REGFLD_EDCR_ED_BURST_DIS            (0x0001UL << 11) /* (RW) Energy Detect Bust Disable */
#define DP83848_REGFLD_EDCR_ED_PWR_STATE            (0x0001UL << 10) /* (RW) Energy Detect Power State */
#define DP83848_REGFLD_EDCR_ED_ERR_MET              (0x0001UL <<  9) /* (RC) Energy Detect Error Threshold Met */
#define DP83848_REGFLD_EDCR_ED_DATA_MET             (0x0001UL <<  8) /* (RC) Energy Detect Data Threshold Met */
#define DP83848_REGFLD_EDCR_ED_ERR_COUNT            (0x000FUL <<  4) /* (RW) Energy Detect Error Threshold*/
#define DP83848_REGFLD_EDCR_ED_DATA_COUNT           (0x000FUL <<  0) /* (RW) Energy Detect Data Threshold */






#endif

