#ifndef RTL8211F_REGS_H
#define RTL8211F_REGS_H

#include "../lip_phy_mdio_regs.h"
#include "../lip_phy_mdio_regs_expage.h"

#define RTL8211F_ID_VENDOR_H        0x001C
#define RTL8211F_ID_VENDOR_L        0x0032
#define RTL8211F_ID_VENDOR          LIP_PHY_VENDOR_ID(RTL8211F_ID_VENDOR_H, RTL8211F_ID_VENDOR_L)
#define RTL8211F_ID_MODEL           0x0011
#define RTL8211F_ID_REVISION        0x000A


#define RTL8211F_REGADDR_INER                               LIP_PHY_REGADDR_EXPAGE(0xa42, 18) /* (RW) Interrupt Enable register */
#define RTL8211F_REGADDR_PHYCR1                             LIP_PHY_REGADDR_EXPAGE(0xa43, 24) /* (RW) PHY Specific Control register 1 */
#define RTL8211F_REGADDR_PHYCR2                             LIP_PHY_REGADDR_EXPAGE(0xa43, 25) /* (RW) PHY Specific Control register 2 */
#define RTL8211F_REGADDR_PHYSR                              LIP_PHY_REGADDR_EXPAGE(0xa43, 26) /* (RO) PHY Specific Status register */
#define RTL8211F_REGADDR_INSR                               LIP_PHY_REGADDR_EXPAGE(0xa43, 29) /* (RO) Interrupt Status register */
#define RTL8211F_REGADDR_PAGSR                              LIP_PHY_REGADDR_EXPAGE(0xa43, 31) /* (RW) Page Select register */
#define RTL8211F_REGADDR_PHYCR3                             LIP_PHY_REGADDR_EXPAGE(0xa44, 17) /* (RW) PHY Specific Control register 3 */
#define RTL8211F_REGADDR_PHYSCR                             LIP_PHY_REGADDR_EXPAGE(0xa46, 20) /* (RW) PHY Special Config register */
#define RTL8211F_REGADDR_PHYSR2                             LIP_PHY_REGADDR_EXPAGE(0xa4b, 16) /* (RO) PHY Specific Status register 2 */
#define RTL8211F_REGADDR_LCR                                LIP_PHY_REGADDR_EXPAGE(0xd04, 16) /* (RW) LED Control register */
#define RTL8211F_REGADDR_EEELCR                             LIP_PHY_REGADDR_EXPAGE(0xd04, 17) /* (RW) EEE LED Control register */
#define RTL8211F_REGADDR_FLCR                               LIP_PHY_REGADDR_EXPAGE(0xd04, 18) /* (RW) Fiber LED Control register */
#define RTL8211F_REGADDR_MIICR1                             LIP_PHY_REGADDR_EXPAGE(0xd08, 17) /* (RW) MII Control register 1 */
#define RTL8211F_REGADDR_MIICR2                             LIP_PHY_REGADDR_EXPAGE(0xd08, 21) /* (RW) MII Control register 2 */
#define RTL8211F_REGADDR_INTBCR                             LIP_PHY_REGADDR_EXPAGE(0xd40, 22) /* (RW) INTB Pin Control register */

#define RTL8211F_REGADDR_PTP_CTL                            LIP_PHY_REGADDR_EXPAGE(0xe40, 16) /* (RW) PTP Control Register */

/******  INER (Interrupt Enable Register, Page 0xa42, Address 0x12) ***********/
#define RTL8211F_REGFLD_INER_JABBER                         (0x0001UL << 10U) /* (RW) Jabber interrupt */
#define RTL8211F_REGFLD_INER_ALDPS_CHANGE                   (0x0001UL <<  9U) /* (RW) ALDPS state changed interrupt */
#define RTL8211F_REGFLD_INER_PME                            (0x0001UL <<  7U) /* (RW) Power Management Event of WOL event occurred interrupt */
#define RTL8211F_REGFLD_INER_PHY_REG_ACCESS                 (0x0001UL <<  5U) /* (RW) PHY registers access interrupt */
#define RTL8211F_REGFLD_INER_LINK_CHANGE                    (0x0001UL <<  4U) /* (RW) Link State Change interrupt */
#define RTL8211F_REGFLD_INER_AUTONEG_CPL                    (0x0001UL <<  3U) /* (RW) Auto-Negotiation Completed interrupt */
#define RTL8211F_REGFLD_INER_PAGE_RECVD                     (0x0001UL <<  2U) /* (RW) Page Received interrupt */
#define RTL8211F_REGFLD_INER_AUTONEG_ERR                    (0x0001UL <<  0U) /* (RW) Auto-Negotiation Error interrupt */
#define RTL8211F_REGMSK_INER_RESERVED                       (0xF942UL)

/******  PHYCR1 (PHY Specific Control Register 1, Page 0xa43, Address 0x18) ***/
#define RTL8211F_REGFLD_PHYCR1_PHYAD0_EN                    (0x0001UL << 13U) /* (RW) Enable broadcast address (PHY address = 0) */
#define RTL8211F_REGFLD_PHYCR1_ALDPS_XTAL_OFF_EN            (0x0001UL << 12U) /* (RW) Enable XTALL off when in ALDPS mode */
#define RTL8211F_REGFLD_PHYCR1_MDI_MODE_CFG_EN              (0x0001UL <<  9U) /* (RW) Enable manual configuration of MDI mode (Soft reset required) */
#define RTL8211F_REGFLD_PHYCR1_MDI_MODE                     (0x0001UL <<  8U) /* (RW) Configured MDI (1)/MDIX (0) mode (if MDI_MODE_CFG_EN = 1) */
#define RTL8211F_REGFLD_PHYCR1_TX_CRS_EN                    (0x0001UL <<  7U) /* (RW) Assert CRS on transmit */
#define RTL8211F_REGFLD_PHYCR1_PHYAD_NONZERO_DET            (0x0001UL <<  6U) /* (RW) When PHYAD[2:0] = 0 latch first non-zero PHY address */
#define RTL8211F_REGFLD_PHYCR1_PREAMPLE_CHECK_EN            (0x0001UL <<  4U) /* (RW) Check preamble when receiving an MDC/MDIO command */
#define RTL8211F_REGFLD_PHYCR1_JABBER_DET_EN                (0x0001UL <<  3U) /* (RW) Jabber detection enable */
#define RTL8211F_REGFLD_PHYCR1_ALDPS_EN                     (0x0001UL <<  2U) /* (RW) Link Power Saving Mode enable */
#define RTL8211F_REGFLD_PHYCR1_ALDPS_PLL_OFF_EN             (0x0001UL <<  1U) /* (RW) Enable PLL of when in ALDPS mode (ALDPS_EN = 1) */
#define RTL8211F_REGMSK_PHYCR1_RESERVED                     (0xCC21UL)

/******  PHYCR2 (PHY Specific Control Register 2, Page 0xa43, Address 0x19) ***/
#define RTL8211F_REGFLD_PHYCR2_CLKOUT_SRC                   (0x0003UL << 12U) /* (RW) Source select of the CLKOUT pin clock output (Soft reset required) */
#define RTL8211F_REGFLD_PHYCR2_CLKOUT_FREQ_SEL              (0x0001UL << 11U) /* (RW) Frequency select of the CLKOUT pin clock output */
#define RTL8211F_REGFLD_PHYCR2_CLKOUT_SSC_EN                (0x0001UL <<  7U) /* (RW) Enable Spread-Spectrum Clocking on CLKOUT pin clock output */
#define RTL8211F_REGFLD_PHYCR2_CENTER_TAP_SHORT_EN          (0x0001UL <<  6U) /* (RW) The transformer center-tap is shorted */
#define RTL8211F_REGFLD_PHYCR2_PHY_MODE_EEE_EN              (0x0001UL <<  5U) /* (RW) Enable EEE in PHY mode */
#define RTL8211F_REGFLD_PHYCR2_SYSCLK_SSC_EN                (0x0001UL <<  3U) /* (RW) Enable Spread-Spectrum Clocking on System Clock */
#define RTL8211F_REGFLD_PHYCR2_RXC_EN                       (0x0001UL <<  1U) /* (RW) RXC clock output enable */
#define RTL8211F_REGFLD_PHYCR2_CLKOUT_EN                    (0x0001UL <<  0U) /* (RW) CLKOUT clock output enable */
#define RTL8211F_REGMSK_PHYCR2_RESERVED                     (0xC714UL)

#define RTL8211F_REGFLDVAL_PHYCR2_CLKOUT_SRC_PLL            0 /* Free run clock generated from internal PLL */
#define RTL8211F_REGFLDVAL_PHYCR2_CLKOUT_UTP_REC            1 /* UTP recovered received clock for Sync Ethernet */
#define RTL8211F_REGFLDVAL_PHYCR2_CLKOUT_FIBER_REC          2 /* FIBER recovered received clock for Sync Ethernet */
#define RTL8211F_REGFLDVAL_PHYCR2_CLKOUT_PTP                3 /* PTP syncronized clock output */

#define RTL8211F_REGFLDVAL_PHYCR2_CLKOUT_FREQ_SEL_25MHZ     0
#define RTL8211F_REGFLDVAL_PHYCR2_CLKOUT_FREQ_SEL_125MHZ    1


/****** PHYSR (PHY Specific Status Register, Page 0xa43, Address 0x1A) ********/
#define RTL8211F_REGFLD_PHYSR_ALDPS_STATE                   (0x0001UL << 14U) /* (RO) Link Down Power Saving Mode */
#define RTL8211F_REGFLD_PHYSR_MDI_PLUG                      (0x0001UL << 13U) /* (RO) MDI Plugged Status */
#define RTL8211F_REGFLD_PHYSR_NWAY_EN                       (0x0001UL << 12U) /* (RO) Auto Negotiation Enable Status*/
#define RTL8211F_REGFLD_PHYSR_MASTER_MODE                   (0x0001UL << 11U) /* (RO) Device in Master (1)/Slave(0) Mode */
#define RTL8211F_REGFLD_PHYSR_EEE_CAPABILITY                (0x0001UL <<  8U) /* (RO) Both partner have EEE capability for current speed */
#define RTL8211F_REGFLD_PHYSR_RX_FLOW_EN                    (0x0001UL <<  7U) /* (RO) Rx flow control enable status */
#define RTL8211F_REGFLD_PHYSR_TX_FLOW_EN                    (0x0001UL <<  6U) /* (RO) Tx flow control enable status */
#define RTL8211F_REGFLD_PHYSR_SPEED                         (0x0003UL <<  4U) /* (RO) Link Speed */
#define RTL8211F_REGFLD_PHYSR_DUPLEX                        (0x0001UL <<  3U) /* (RO) Full Duplex Mode */
#define RTL8211F_REGFLD_PHYSR_LINK_RT                       (0x0001UL <<  2U) /* (RO) Real Time Link Status */
#define RTL8211F_REGFLD_PHYSR_MDI_CROSS                     (0x0001UL <<  1U) /* (RO) MDI Crossover Status (1 - MDI, 0 - MDI Cross) */
#define RTL8211F_REGFLD_PHYSR_JABBER_RT                     (0x0001UL <<  0U) /* (RO) Real Time Jabber Status */

#define RTL8211F_REGFLDVAL_PHYSR_SPEED_10                   0 /* 10 Mbit/s */
#define RTL8211F_REGFLDVAL_PHYSR_SPEED_100                  1 /* 100 Mbit/s */
#define RTL8211F_REGFLDVAL_PHYSR_SPEED_1000                 2 /* 1000 Mbit/s */


/****** INSR (Interrupt Status Register, Page 0xa43, Address 0x1D) ************/
#define RTL8211F_REGFLD_INSR_JABBER                         (0x0001UL << 10U) /* (RC) Jabber interrupt */
#define RTL8211F_REGFLD_INSR_ALDPS_CHANGE                   (0x0001UL <<  9U) /* (RC) ALDPS state changed interrupt */
#define RTL8211F_REGFLD_INSR_PME                            (0x0001UL <<  7U) /* (RC) Power Management Event of WOL event occurred interrupt */
#define RTL8211F_REGFLD_INSR_PHY_REG_ACCESS                 (0x0001UL <<  5U) /* (RC) PHY registers access interrupt */
#define RTL8211F_REGFLD_INSR_LINK_CHANGE                    (0x0001UL <<  4U) /* (RC) Link State Change interrupt */
#define RTL8211F_REGFLD_INSR_AUTONEG_CPL                    (0x0001UL <<  3U) /* (RC) Auto-Negotiation Completed interrupt */
#define RTL8211F_REGFLD_INSR_PAGE_RECVD                     (0x0001UL <<  2U) /* (RC) Page Received interrupt */
#define RTL8211F_REGFLD_INSR_AUTONEG_ERR                    (0x0001UL <<  0U) /* (RC) Auto-Negotiation Error interrupt */
#define RTL8211F_REGMSK_INSR_RESERVED                       (0xF942UL)


/****** PAGSR (Page Select Register, Page 0xa43, Address 0x1F) ****************/
#define RTL8211F_REGFLD_PAGSR_PAGESEL                       (0x0FFFUL <<  0U) /* (RW) Page select */
#define RTL8211F_REGMSK_PAGSR_RESERVED                      (0xF000UL)


/****** PHYCR3 (PHY Specific Control Register 3, Page 0xa44, Address 0x11) ****/
#define RTL8211F_REGFLD_PHYCR3_RETRY_SPDN_THR               (0x0001UL <<  4U) /* (RW) Retry time before speed down */
#define RTL8211F_REGFLD_PHYCR3_RETRY_SPDN_EN                (0x0001UL <<  3U) /* (RW) Enable retry speed down */
#define RTL8211F_REGFLD_PHYCR3_2PAIR_SPDN_EN                (0x0001UL <<  2U) /* (RW) Enable two-pair speed down */
#define RTL8211F_REGMSK_PHYCR3_RESERVED                     (0xFFE3UL)

#define RTL8211F_REGFLDVAL_PHYCR3_RETRY_SPDN_THR_3          1 /* 3 times */
#define RTL8211F_REGFLDVAL_PHYCR3_RETRY_SPDN_THR_7          0 /* 7 times */


/****** PHYSCR (PHY Specific Config Register, Page 0xa46, Address 0x14) *******/
#define RTL8211F_REGFLD_PHYSCR_PHY_SPEC_CFG_DONE            (0x0001UL <<  1U) /* (RW1) Write 1 to indicate special config done */
#define RTL8211F_REGMSK_PHYSCR_RESERVED                     (0xFFFDUL)


/****** PHYS2R (PHY Specific Status Register 2, Page 0xa4b, Address 0x10) *****/
#define RTL8211F_REGFLD_PHYSR2_RETRY_SPDN_LINKOK            (0x0001UL << 12U) /* (RO LH SC) Linkok due to retry speed down */
#define RTL8211F_REGFLD_PHYSR2_2PAIR_SPDN_LINKOK            (0x0001UL << 11U) /* (RO LH SC) Linkok due to two-pair speed down */
#define RTL8211F_REGMSK_PHYSR2_RESERVED                     (0xE7FFUL)


/****** LCR (LED Control Register, Page 0xd04, Address 0x10) ******************/
#define RTL8211F_REGFLD_LCR_LED_ACT(n)                      (0x0001UL << ( 4U + 5*(n))) /* (RW) LEDn activity (tx/rx) indication, n = 0..2 */
#define RTL8211F_REGFLD_LCR_LED_LINK_1000(n)                (0x0001UL << ( 3U + 5*(n))) /* (RW) LEDn link 1000Mbps indication, n = 0..2 */
#define RTL8211F_REGFLD_LCR_LED_LINK_100(n)                 (0x0001UL << ( 1U + 5*(n))) /* (RW) LEDn link 100Mbps indication, n = 0..2 */
#define RTL8211F_REGFLD_LCR_LED_LINK_10(n)                  (0x0001UL << ( 0U + 5*(n))) /* (RW) LEDn link 10Mbps indication, n = 0..2 */
#define RTL8211F_REGMSK_LCR_RESERVED                        (0x9084UL)


/****** EEELCR (EEE LED Control Register, Page 0xd04, Address 0x11) ***********/
#define RTL8211F_REGFLD_EEELCR_LED_EEE_EN(n)                (0x0001UL << ( 1U + (n)))   /* (RW) LEDn EEE indication, n = 0..2 */
#define RTL8211F_REGMSK_EEELCR_RESERVED                     (0xFFF1UL)


/****** FLCR (Fiber LED Control Register, Page 0xd04, Address 0x12) ***********/
#define RTL8211F_REGFLD_FLCR_LED_COMMON_MODE(n)             (0x0001UL << (11U + 2*(n))) /* (RW) LEDn common mode indication, n = 0..2 */
#define RTL8211F_REGFLD_FLCR_LED_MEDIA_SELECT(n)            (0x0001UL << (10U + 2*(n))) /* (RW) LEDn media selection indication (0 - UTP, 1 - SERDES), n = 0..2 */
#define RTL8211F_REGMSK_FLCR_RESERVED                       (0x03FFUL)


/****** MIICR1 (MII Control Register 1, Page 0xd08, Address 0x11) *************/
#define RTL8211F_REGFLD_MIICR1_TXDLY_EN                     (0x0001UL <<  8U) /* (RW) Enable RGMII TXDLY */
#define RTL8211F_REGMSK_MIICR1_RESERVED                     (0xFEFFUL)


/****** MIICR2 (MII Control Register 2, Page 0xd08, Address 0x15) *************/
#define RTL8211F_REGFLD_MIICR2_INBAND_CRS_EN                (0x0001UL <<  6U) /* (RW) Enable in-band CRS Status in RGMII Rx flow */
#define RTL8211F_REGFLD_MIICR2_RXDLY_EN                     (0x0001UL <<  3U) /* (RW) Enable RGMII RXDLY */
#define RTL8211F_REGMSK_MIICR2_RESERVED                     (0xFFB7L)


/****** INTBCR (INTB Pin Control Register, Page 0xd40, Address 0x16) **********/
#define RTL8211F_REGFLD_INTBCR_INTB_PMEB_SEL                (0x0001UL <<  5U) /* (RW) Select PIN 34 function as PMEB */
#define RTL8211F_REGFLD_INTBCR_INTB_PTP_GPIO1_SEL           (0x0007UL <<  0U) /* (RW) Select PIN 34 function as PTP_GPIO1 (=5) */
#define RTL8211F_REGFLD_INTBCR_RESERVED                     (0xFFD8UL)

#define RTL8211F_REGFLDVAL_INTBCR_INTB_PTP_GPIO1_SEL        5 /* PTP_GPIO1 */



/****** PTP_CTL (PTP Control Register, Page 0xe40, Address 0x10) **************/
#define RTL8211F_REGFLD_PTP_CTL_UDP_CHKSUM_UPD              (0x0001UL << 12U) /* (RW) Enable IPV6/UDP Checksum Autocorrection if One-Stamp Timestamp insertion enabled */
#define RTL8211F_REGFLD_PTP_CTL_P_DRFU_2STEP_INS            (0x0001UL << 11U) /* (RW) Enable hardware-assisted timestamp insertion to PDelay_Resp_Follow_Up messages */
#define RTL8211F_REGFLD_PTP_CTL_P_DR_2STEP_INS              (0x0001UL << 10U) /* (RW) Enable hardware-assisted timestamp insertion to PDelay_Resp messages */
#define RTL8211F_REGFLD_PTP_CTL_DR_2STEP_INS                (0x0001UL <<  9U) /* (RW) Enable hardware-assisted timestamp insertion to PDelay_Resp messages */



#endif // RTL8211F_REGS_H
